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dm9801 1m home phoneline network physical layer single chip transceiver preliminary 1 version: dm9801-ds-p02 march 20, 2000 general description the dm9801 is a physical-layer, single-chip, low-power transceiver for 1m home phoneline network applications. on the media side, it provides an interface to a home phoneline wiring system. the reconciliation layer interfaces to the dm9801 either through an ieee802.3u subset media independent interface (mii) or a pseudo-standard general purpose serial interface (gpsi). a management interface is provided by mdio/mdc when operating in mii mode, or a serial peripheral interface bus when operating in gpsi mode. the dm9801 uses a low-power and high-performance cmos process. it contains the entire physical layer functions of 1m as defined by home phoneline network alliance, rev. 1.1, including the physical coding sublayer, (rll25) encoder/decoder (enc/dec), 4-wire hn driver circuit and receiver analog front end (afe). patent-pending circuitry includes: an enhanced 4-wire home network transceiver circuit. block diagram hn secondary driver muxed gpsi or mii interface rll25 encoder rll25 decoder master phy controller receiever and digital pll transmit timing generator hn primary driver receiver afe gpsi - mii transmit gpsi - mii receive hna+/- hnb+/- interface select
dm9801 1m home phoneline network physical layer single chip transceiver 2 preliminary version: dm9801-ds-p02 march 20, 2000 features ? 1m home phoneline network physical-layer, single- chip transceiver ? supports the mii including the mdio/mdc serial management interface ? supports the gpsi including a spi serial management interface ? supports link integrity function ? smart equalizer circuit for 1m receiver ? supports patent pending 4-wire operation ? supports hardware or software speed select ? supports interrupt on change, eliminates management polling ? flexible built-in led support for tx activity, rx activity and collision indication or activity, link state and collision ? digital pll circuit using advanced digital algorithm to reduce jitter ? low-power, high-performance cmos process ? available in a small outline 100-pin lqfp ? 3.3v dc power with 5v dc tolerant i/o
dm9801 1m home phoneline network physical layer single chip transceiver preliminary 3 version: dm9801-ds-p02 march 20, 2000 pin configuration: dm9801, 100-pin lqfp 36 DM9801E 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 rxd0(srxdat) rxd1 rxd2 rxd3 crs rx_dv(so) col(clsn) rx_clk(srdclk) dgnd tx_clk(stdclk) txd0(stxdat txd1(bp1) txd2(si) tx_en(stxen) 26 27 28 29 30 31 32 33 34 35 37 38 39 40 41 42 43 44 45 46 47 48 49 50 dvcc dvcc phyad0 mdio(scs#) mdc(bp0) tridrv reset# config1 intfsel cmdena spdsel pwsel fwena dgnd tstmode dvcc nc int# lnksta colled# rxled#(lnkled#) txled#(actled#) dgnd avcc bgref bggnd agnd hnpa hnna xtal1 xtal2 51 nc nc nc phyad3 phyad2 phyad1 nc nc nc nc nc nc nc nc nc nc agnd nc nc nc avcc avcc nc agnd agnd hnpb hnnb nc avcc nc phyad4 dgnd nc nc nc nc nc nc config0 nc nc nc nc nc nc nc nc dgnd nc 81 txd3(smode) nc nc nc nc nc
dm9801 1m home phoneline network physical layer single chip transceiver 4 preliminary version: dm9801-ds-p02 march 20, 2000 pin description pin no. pin name i/o description station interface: receive data, transmit data and management 85 txd0 or stxdat i transmit data bit 0 (mii mode, intfsel = 0): transmit data input pin, bit 0, for nibble data from the mii serial transmit data bit (gpsi mode, intfsel = 1): transmit data input pin for serial data from the gpsi. 84 txd1 or bp1 i transmit data bit 1 (mii mode, intfsel = 0): transmit data input pin, bit 1, for nibble data from the mii sprom boot page select 1 (gpsi mode, intfsel = 1): most significant bit of a 2-bit encoded select. the bp1 and bp0 inputs, select one of four, 64-byte, sprom pages to initialize the dm9801 management registers. master mode must be selected using the smode input. 83 txd2 or si i transmit data bit 2 (mii mode, intfsel = 0): transmit data input pin, bit 2, for nibble data from the mii serial data input (gpsi mode, intfsel = 1): this is the serial data input pin to the dm9801 for the spi bus. the spi bus operation is only valid if gpsi mode is selected. 82 txd3 or smode i transmit data bit 3 (mii mode, intfsel = 0): transmit data input pin, bit 3, for nibble data from the mii serial mode select (gpsi mode, intfsel = 1): this input pin selects the spi buses mode of operation. the spi bus modes of operation are: master mode (smode = 0) slave mode (smode = 1) the spi bus operation is only valid if gpsi mode is selected. 86 tx_clk or stdclk o,z mii transmit clock (mii mode, intfsel = 0): tx_clk is an output pin from the dm9801. used as the transmit data reference clock, to clock in nibble data from the mii when in mii interface mode. serial transmit data clock (gpsi mode, intfsel = 1): stdclk is an output from the dm9801. used as the transmit reference clock to clock in the stxdata when in gpsi interface mode. 81 tx_en or stxen i mii transmit enable (mii mode, intfsel = 0): mii transmit enable input, used to enable the transmit function of the mii when in mii interface mode. serial transmit enable (gpsi mode, intfsel = 1): used to enable the transmit functi on of the gpsi when in gpsi interface mode. 66 mdc or bp0 i mii serial management clock (mii mode, intfsel = 0): synchronous clock to the mdio management data input/output serial interface which is asynchronous to transmit and receive clocks. the maximum clock rate is 2.5mhz. sprom boot page select 0 (gpsi mode, intfsel = 1): least significant bit of a 2-bit encoded select. the bp1 and bp0 inputs, select one of four, 64-byte, sprom pages to initialize the dm9801 management registers. master mode must be selected using the smode input.
dm9801 1m home phoneline network physical layer single chip transceiver preliminary 5 version: dm9801-ds-p02 march 20, 2000 pin description (continued) pin no. pin name i/o description station interface: receive data, transmit data and management (continued) 67 mdio or scs# i/o,z mii serial management data (mii mode, intfsel = 0): bi-directional management instruction/data signal that may be driven by the station management entity or the phy. this pin requires a 1.5k ? pull-up resistor. serial interface chip select (gpsi mode, intfsel = 1): scs# is a bi-directional management chip select signal that may be driven by the station management entity or the phy. (active low) 97 rxd0 or srxdat o,z receive data bit 0 (mii mode, intfsel = 0): receive data output pin, bit 0, for nibble data to the mii serial receive data bit (gpsi mode, intfsel = 1): receive data output pin for serial data to the gpsi. 96 rxd1 o,z receive data bit 1: receive data output pin, bit 1, for nibble data to the 95 rxd2 o,z receive data bit 2: receive data output pin, bit 2, for nibble data to the mii 94 rxd3 o,z receive data bit 3: receive data output pin, bit 3, for nibble data to the mii 90 rx_clk or srdclk o,z mii receive clock (mii mode, intfsel = 0): rx_clk is an output pin from the dm9801. used as the receive data reference clock, to clock out nibble data from the mii when in mii interface mode. serial receive data clock (gpsi mode, intfsel = 1): srdclk is an output from the dm9801. used as the receive reference clock to clock out the srxdata when in gpsi interface mode. 91 rx_dv or so o,z receive data valid (mii mode, intfsel = 0): rx_dv is asserted high to indicate that valid data is present on rxd[3:0]. serial data output (gpsi mode, intfsel = 1): this is the serial data output pin from the dm9801 for the spi bus. the spi bus operation is only valid if gpsi mode is selected. 93 crs o,z carrier sense: this pin is asserted high to indicate the presence of carrier due to receive or transmit activities. 92 col or clsn o,z collision detect mii mode, intfsel = 0): col is asserted high to indicate detection of collision condition. collision detect (gpsi mode, intfsel = 1): clsn is asserted high to indicate detection of collision condition.
dm9801 1m home phoneline network physical layer single chip transceiver 6 preliminary version: dm9801-ds-p02 march 20, 2000 pin description (continued) phy address interface: phyad[4:0] provides up to 32 unique phy address. an address selection of all zeros (00000) will result in a phy isolation condition. see the isolate bit description in the bmcr, address 00. 68 phyadsel (phyad0) or sclk i/o,z mii serial management phy address select (mii mode, intfsel = 0): phyadsel is an input signal that selects one of two phy addresses within the 32 address range for the dm9801 mii management interface when both config1 and config0 are not set to 1. 0 = 0x01 address 1 = 0x1f address phy address 0 (mii mode, intfsel = 0): phy address bit 0 for multiple phy address applications. both config1 and config0 must be set to 1. serial interface clock (gpsi mode, intfsel = 1): sclk is a bi-directional clock signal used to synchronize si, so and scs# to and from the dm9801 spi bus. 8 phyad1 i/o, z phy address 1 (mii mode, intfsel = 0): phy address bit 1 for multiple phy address applications. both config1 and config0 must be set to 1. leave unconnected when both config1 and config0 are not 1. 9 phyad2 i/o, z phy address 2 (mii mode, intfsel = 0): phy address bit 2 for multiple phy address applications. both config1 and config0 must be set to 1. leave unconnected when both config1 and config0 are not 1. 10 phyad3 i/o, z phy address 3 (mii mode, intfsel = 0): phy address bit 3 for multiple phy address applications. both config1 and config0 must be set to 1. leave unconnected when both config1 and config0 are not 1. 47 phyad4 i/o, z phy address 4 (mii mode, intfsel = 0): phy address bit 4 for multiple phy address applications. both config1 and config0 must be set to 1. leave unconnected when both config1 and config0 are not 1.
dm9801 1m home phoneline network physical layer single chip transceiver preliminary 7 version: dm9801-ds-p02 march 20, 2000 pin description (continued) pin no. pin name i/o description configuration and control interface: 64 reset# i reset: active low input that initializes the dm9801. should remain low for 10ms after vcc has stabilized at 3.3vdc (nominal) before it transitions high. 63 62 config0 config1 i configuration select 1:0: these input pins select the dm9801 configuration from a reset condition. config1 config0 configuration selected 0 0 txled, rxled and colled configuration * 0 1 actled, lnkled and colled configuration * 1 0 actled, lnkled and colled configuration with mii management register 0-6 emulation support * 1 1 actled, lnkled and colled configuration with mii management register 0-6 emulation and 32 phy addresses support *see the dm9801 description for a more detailed explanation 61 intfsel i interface select: this pin selects either the mii interface or the gpsi interface. 0 = mii 1 = gpsi 60 cmdena i command enable: this pin enables a remote master node to alter the management register values of the local dm9801. 59 spdsel i speed select: this pin will select the 1m network speed. 0 = low speed 1 = high speed 58 pwrsel i power select: this pin will select the 1m network power. 0 = low power 1 = high power 65 tridrv i tri-state all outputs: this pin, when asserted high, will tri-state all outputs (no effect on open- drain outputs). 57 fwena i four wire interface enable: this pin, when asserted high, will enable the hnpb and hnnb driver pair for operation. when low, the secondary drivers are powered down. 6 int# od interrupt request: this pin will be asserted low when an interrupt condition exists in the dm9801.
dm9801 1m home phoneline network physical layer single chip transceiver 8 preliminary version: dm9801-ds-p02 march 20, 2000 pin description (continued) pin no. pin name i/o description led interface : these outputs can directly drive leds or provide status information to a network management device. 13 txled# or actled# od transmit led: indicates the dm9801 is transmitting data (active low, open drain). config0 = 0 and config1 = 0 activity led: indicates the dm9801 is either transmitting or receiving data (active low, open drain). 12 rxled# or lnkled# od receive led: indicates the presence of receive data activity by the dm9801(active low, open drain). config0 = 0 and config1 = 0 link led: indicates good link status and that the link integrity timer has not expired (active low, open drain). 11 colled# od collision led: indicates the presence of collision activity on the 1m network (active low, open drain). home phoneline network media interface: 36 hnpa alg home network interface, positive, primary: this is the positive interface connection of the primary 1m network interface. 37 hnna alg home network interface, negative, primary: this is the negative interface connection of the primary 1m network interface. 40 hnpb alg home network interface, positive, secondary: this is the positive interface connection of the secondary 1m network interface. 41 hnnb alg home network interface, negative, secondary: this is the negative interface connection of the secondary 1m network interface.
dm9801 1m home phoneline network physical layer single chip transceiver preliminary 9 version: dm9801-ds-p02 march 20, 2000 pin description (continued) pin no. pin name i/o description miscellaneous: 7 lnksta i/o,z link status: output, positive true logic. indication of link status. 45 xtal1 alg crystal pin 1: this pin should be connected to one side of a 20mhz ( 50 ppm) crystal. 46 xtal2 alg crystal pin 2: this pin should be connected to the other side of a 20mhz ( 50 ppm) crystal. 21 bgref alg bandgap voltage reference: connect a 6.20_k ? , 1% resistor between this pin and the bggnd pin to provide an accurate current reference for the dm9801. 22 bggnd alg bandgap voltage reference return: return pin for the 6.20_k ? resistor connection. 53 tstmode i test mode control pin: tstmode=0: normal operating mode. tstmode=1: enable test mode. 1, 2, 3,5, 15 ? 18, 20, 23 ? 27, 30 - 32, 35, 42, 44, 49 ? 52, 54, 56, 69, 70, 73 ? 78, 80, 87, 89, 98, 99, 100 nc no connect: these pins are reserved. leave these pins unconnected (floating). power and ground: the power (vcc) and ground (gnd) pins of the dm9801 are grouped in pairs of two categories - digital circuitry power/ground pairs and analog circuitry power/ground pair. 14, 48, 55, 79, 88, dgnd p digital logic ground 4, 71, 72 dvcc p digital logic power supply 28, 29, 38, 39 agnd p analog circuit ground 19, 33, 34, 43 avcc p analog circuit power supply
dm9801 1m home phoneline network physical layer single chip transceiver 10 preliminary version: dm9801-ds-p02 march 20, 2000 functional description the dm9801 is a single-chip home phoneline network transceiver .the dm9801 provides an ieee 802.3u subset media independent interface (mii) or a pseudo- standard general purpose serial interface (gpsi). the dm9801 enables home networking by allowing ethernet packets to be transported over common home telephone wiring with no modifications, using ethernet csma/cd media access control procedures as defined in the ieee 802.3 standard. figure 1 shows the major functional blocks implemented in the dm9801. figure 1 mii interface the dm9801 provides a subset media independent interface (mii) or a pseudo-standard general purpose serial interface (gpsi). the mii interface provides a simple, easy way to implement connection between the mac reconciliation layer and the dm9801 transceiver. the mii is designed to make the differences between various media transparent to the mac sublayer. the mii consists of a nibble wide receive data bus, a nibble wide transmit data bus, and control signals to facilitate data transfers between the phy and the reconciliation layer. txd (transmit data) is a nibble (4 bits) of data that are driven by the reconciliation sublayer synchronously with respect to tx_clk. for each tx_clk period, which tx_en is asserted, txd (3:0) are accepted for transmission by the phy. tx_clk (transmit clock) output to the mac reconciliation sublayer is a clock that provides the timing reference for the transfer of the tx_en, txd, and tx_er signals. tx_en (transmit enable) input from the mac reconciliation sublayer to indicate nibbles are being presented on the mii for transmission on the physical medium. muxed gpsi or mii interface rll25 encoder rll25 decoder master phy controller receiver and digital pll receiver afe hn drivers transmit timing generator
dm9801 1m home phoneline network physical layer single chip transceiver preliminary 11 version: dm9801-ds-p02 march 20, 2000 mii interface (continued) rxd (receive data) is a nibble (4 bits) of data that are sampled by the reconciliation sublayer synchronously with respect to rx_clk. for each rx_clk period that rx_dv is asserted, rxd (3:0) are transferred from the phy to the mac reconciliation sublayer. rx_clk (receive clock) output to the mac reconciliation sublayer is a clock that provides the timing reference for the transfer of the rx_dv, rxd, and rx_er signals. rx_dv (receive data valid) input from the phy to indicate the phy is presenting recovered and decoded nibbles to the mac reconciliation sublayer. to interpret a receive frame correctly by the reconciliation sublayer, rx_dv must encompass the frame starting no later than the start- of-frame delimiter and excluding any end-stream delimiter. crs (carrier sense) is asserted by the phy when either the transmit or receive medium is non-idle and deasserted by the phy when the transmit and receive medium are idle. mii serial management the mii serial management interface consists of a data interface, basic register set, and a serial management interface to the register set. through this interface it is possible to control and configure multiple phy devices, get status and error information, and determine the type and capabilities of the attached phy device(s). mii interface transmit and receive timing diagram the dm9801 management functions correspond to mii specification for ieee 802.3u-1995 (clause 22) for registers 0 through 6 with vendor-specific registers 16 through 31. in read/write operation, the management data frame is 64-bits long and starts with 32 contiguous logic one bits (preamble) synchronization clock cycles on mdc. the start of frame delimiter (sfd) is indicated by a <01> pattern followed by the operation code (op):<10> indicates read operation and <01> indicates write operation. for read operation, a 2-bit turnaround (ta) filing between register address field and data field is provided for mdio to avoid contention. following the turnaround time, 16-bit data is read from or written to the management registers. serial management interface the serial control interface uses a simple two-wired serial interface to obtain and control the status of the physical layer through the mii interface. the serial control interface consists of mdc (management data clock), and mdi/o (management data input/output) signals. the mdio pin is bi-directional and may be shared by up to 32 devices. tx_clk rx_clk tx_en txd crs rxd col rx_dv 0 0 rx_clk and tx_clk are synchronized. all signals are inactive. the period of the two clock is 2333.3 ns. idle state figure 2
dm9801 1m home phoneline network physical layer single chip transceiver 12 preliminary version: dm9801-ds-p02 march 20, 2000 mii interface transmit and receive timing diagram (continued) tx_clk rx_clk tx_en txd crs rxd col rx_dv 0 0 rx_clk becomes disabled (and left in the low state) as soon as crs is asserted. the clock is re-enabled about 140 us into the packet. rxpkt ? crs asserted figure 3 tx_clk rx_clk tx_en txd crs rxd col rx_dv 5 (preamble) data 0 000 0 rx_clk and tx_clk are unrelated to each other during this time. when a symbol has been received and decoded, rx_clk toggles at various frequencies depending on what data have been received. once crs falls, rx_clk and tx_clk are toggled continuously at 933.3 ns for 22 cycles, after which dm9801 returns to the idle state. rxpkt ? rx_clk active and crs cleared figure 4
dm9801 1m home phoneline network physical layer single chip transceiver preliminary 13 version: dm9801-ds-p02 march 20, 2000 mii interface transmit and receive timing diagram (continued) tx_clk rx_clk tx_en txd crs rxd col rx_dv 0 5 (preamble) d 0 data once tx_en is asserted, dm9801 stops rx_clk, asserts crs, and toggles tx_clk at 933.3 ns. txpkt ? tx_en asserted figure 5 tx_clk rx_clk tx_en txd crs rxd col rx_dv d data 5 (preamble) 0 data 5 d tx_clk continues to toggle at 933.3 ns until the sfd is observed, as shown in the first section of the above diagram. at this point, tx_clk is disabled (high) until aid header has been transmitted on the wire (or until a col has been detected). this takes about 120 us, at which time rx_clk starts toggling, ther eby shifting 32 bits of preamble and sfd back to the mac. sometime later, the tx_clk restarts as symbols get sent onto the wire in an analogous manner as rx_clk during packet reception. txpkt ? rx_clk active figure 6
dm9801 1m home phoneline network physical layer single chip transceiver 14 preliminary version: dm9801-ds-p02 march 20, 2000 mii interface transmit and receive timing diagram (continued) tx_clk rx_clk tx_en txd crs rxd col rx_dv data data 0 0 once tx_en is cleared, the last symbol gets encoded and transmitted, the looped-back data is presented back to the mac, and crs falls. once crs falls, tx_clk and rx_clk toggles with a period of 933.3 ns for 22 clocks, after which the system returns to the idle state. txpkt ? tx_en cleared figure 7 tx_clk rx_clk tx_en txd crs rxd col rx_dv 5 0 0 d data 0 col will be asserted sometime after the preamble and sfd have been clocked in. tx_clk and rx_clk are then clocked with a period 933.3 ns until crs drops. tx_en drops sometime after col was asserted. crs and col are dropped after more than 80 clocks. tx_clk and rx_clk keep toggling at 933.3 ns period for roughly another 25 clock cycles, when the system returns to the idle state. txpkt ? col asserted figure 8
dm9801 1m home phoneline network physical layer single chip transceiver preliminary 15 version: dm9801-ds-p02 march 20, 2000 mii interface transmit and receive timing diagram (continued) tx_clk rx_clk tx_en txd crs rxd col rx_dv 0 0 0 0 col may be asserted up to 120 us after crs has been asserted. once col has been asserted, tx_clk and rx_clk run at a period of 933.3 ns until col and crs are cleared. it can take up to about 600 us for crs to clear. rxpkt ? col asserted figure 9 management interface - read frame structure 32 "1"s 0 1 1 0 a4 a3 a0 r4 r3 r0 z 0 idle preamble sfd op code phy address register address turn around data idle read write mdc mdio read d15 d14 d1 d0 // // management interface - write frame structure 32 "1"s 0 1 1 0 a4 a3 a0 r4 r3 r0 1 0 d15 d14 d1 d0 idle preamble sfd op code phy address register address turn around data idle write mdc mdio write figure 10
dm9801 1m home phoneline network physical layer single chip transceiver 16 preliminary version: dm9801-ds-p02 march 20, 2000 general purpose serial interface the dm 9801 provides a subset media independent interface (mii) or a pseudo-standard general purpose serial interface (gpsi). the gpsi interface provides a simple, easy way to implement connection between the mac reconciliation layer and the dm9801 transceiver. the gpsi is designed to make the differences between various media transparent to the mac sublayer. the gpsi interface provides a serial receive data bus, a serial transmit data bus, and control signals to facilitate data transfers between the dm9801 transceiver and the reconciliation layer. the seven signals which comprise the gpsi are stxdat, stdclk, stxen, srxdat, srxclk, clsn, and crs. of these, only stxen and stxdat are inputs to the dm9801, the other five are outputs from the dm9801. stxdat (serial transmit data) is a serial stream of data that are driven by the reconciliation sublayer synchronously with respect to stdclk. for each stdclk period, which stxen is asserted, stxdat is accepted for transmission by the phy. stdclk (serial transmit data clock) is an output to the mac reconciliation sublayer. stdclk is a clock that provides the timing reference for the transfer of the stxdat in gpsi mode. stxen (serial transmit enable) input from the mac reconciliation sublayer to indicate serial data is being presented on the gpsi for transmission on the physical medium. srxdat (serial receive data) is a serial stream of data that is sampled by the reconciliation sublayer synchronously with respect to srxclk. srxclk (serial receive data clock) is an output to the mac reconciliation sublayer. srdclk is a clock that provides the timing reference for the transfer of the srxdat in gpsi mode. clsn (collision detect) is an output to the mac reconciliation sublayer. clsn is asserted high to indicate detection of collision condition crs (carrier sense) is an output to the mac reconciliation sublayer that is asserted high to indicate the presence of carrier due to receive or transmit activities. the subsequent sections analyze each gpsi related state of the dm9801 in detail. stdclk srdclk stxen stxdat crs srxdat clsn srdclk and stdclk are synchronized. all other signals are inactive. idle state figure 11
dm9801 1m home phoneline network physical layer single chip transceiver preliminary 17 version: dm9801-ds-p02 march 20, 2000 general purpose serial interface (continued) stdclk srdclk stxen stxdat crs srxdat clsn srdclk becomes disabled as soon as crs is asserted. rxpkt- crs asserted figure 12 stdclk srdclk stxen stxdat crs srxdat clsn srdclk and stdclk are unrelated to each other during this time. when a symbol has been received and decoded, srdclk toggles in order to shift out the three to six bits encoded in the symbol. the middle portion of this diagram shows the end of the preamble, followed by the sfd and the beginning of the datagram. crs will fall after the last received symbol. once crs falls, srdclk and stdclk are toggled continuously for 97 cycles after which the dm9801 returns to the idle state. rxpkt - srdclk active and crs cleared figure 13
dm9801 1m home phoneline network physical layer single chip transceiver 18 preliminary version: dm9801-ds-p02 march 20, 2000 general purpose serial interface (continued) stdclk srdclk stxen stxdat crs srxdat clsn once stxen is asserted, the dm9801 stops srdclk, asserts crs, and toggles stdclk. txpkt - stxen asserted figure 14 stdclk srdclk stxen stxdat crs srxdat clsn stdclk continues to toggle until sfd is observed, as shown in the first section on the above diagram. at this point, stdclk is disabled until the aid header has been transmitted on the wire or until cls has been detected. at this time srdclk starts toggling, thereby shifting 32 bits of preamble and sfd back to th e mac. sometime later, the stdclk restarts as symbols get sent onto the wire in an analogous manner as srdclk during packet reception. txpkt - srdclk active figure 15
dm9801 1m home phoneline network physical layer single chip transceiver preliminary 19 version: dm9801-ds-p02 march 20, 2000 general purpose serial interface (continued) stdclk srdclk stxen stxdat crs srxdat clsn once stxen is cleared, the last symbol gets encoded and transmitted. the looped-back data is presented back to the mac and sometime later crs falls. once crs falls, stdclk and srdclk toggle for 97 clocks after which the system returns to the idle state. txpkt - stxen cleared figure 16 stdclk srdclk stxen stxdat crs srxdat clsn clsn will be asserted some time after the preamble and sfd have been clocked in. stdclk and srdclk are then clocked until crs drops. stxen drops sometime after clsn was asserted. crs and clsn are dropped together after more than 500 clocks. stdclk and srdclk keep toggling for approximately another 100 clock cycles, then the system returns to the idle state. txpkt - clsn asserted figure 17
dm9801 1m home phoneline network physical layer single chip transceiver 20 preliminary version: dm9801-ds-p02 march 20, 2000 general purpose serial interface (continued) stdclk srdclk stxen stxdat crs srxdat clsn clsn may be asserted up to 120us after crs has been asserted. once clsn has been asserted stdclk and srdclk run at a period of 233.3ns per cycle until 97 cycles after clsn and crs are cleared. it can take up to about 60us for crs to clear. rxpkt - clsn cleared figure 18
dm9801 1m home phoneline network physical layer single chip transceiver preliminary 21 version: dm9801-ds-p02 march 20, 2000 serial peripheral interface (spi) bus when intfsel is asserted, the dm9801 is configured to operate in spi mode. while configured to operate in spi mode, the dm9801 can act as a spi slave or spi master. asserting smode places the dm9801 in spi slave mode. clearing smode places the dm9801 in spi master mode. the spi (serial peripheral interface) bus uses a four-wired serial interface to obtain and control the status of the physical layer through the spi bus interface. the serial control interface consists of si (serial data input), so (serial data output), sclk (serial clock), and scs# (serial interface chip select) signals. when operating in master mode the dm9801 drives the sclk and scs# signals, when operating in slave mode these signals are inputs. spi-slave mode (valid only in gpsi mode) when smode is asserted the dm9801 is configured for spi slave operation. commands are issued to the dm9801 by asserting the scs# signal, shifting in an 8-bit opcode followed by a register address and an end delimiter. if the operation is a write, the address is followed by an 8- bit data byte. if the operation is a read, the so pin will shift out an 8-bit data byte representing the contents of the register referenced by the address field. only one command can be sent in one scs# cycle. the dm9801 does not support multiple byte reads or writes. spi-master mode (valid only in gpsi mode) when smode is cleared the dm9801 is configured for spi master operation. when the dm9801 is configured for spi-master oper ation, it will load all programmable registers from an external spi type eeprom. the memory locations loaded may be offset via the boot page pins, bp[1:0], allowing a single 256 byte serial eeprom to hold four distinct sets of default register values. after reset# has cleared the dm9801 will assert scs#, shift out a read opcode (0x03), followed by the initial address to be read (as modified by the boot page pins). the dm9801 will then shift in the memory contents, auto incrementing the register address being programmed every 8-bits. once all 64-bytes have been read, the dm9801 releases scs#. the sclk continues to run. opcodes are shown in table 1. instruction format instruction name 0000 0110 set we 0000 0100 clear we 0000 0011 read 0000 0010 write opcodes table 1
dm9801 1m home phoneline network physical layer single chip transceiver 22 preliminary version: dm9801-ds-p02 march 20, 2000 serial peripheral interface (spi) bus (continued) sclk so scs# si b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 instruction byte address byte data byte 0 b7 b6 spi master mode timing figure 19 sclk si scs# so b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 instruction byte address byte data byte (high-z when writing) (don't care on read) data byte spi slave mode timing figure 20
dm9801 1m home phoneline network physical layer single chip transceiver preliminary 23 version: dm9801-ds-p02 march 20, 2000 mii serial management register map (intfsel = 0, mii mode) register address register name access type default value description 0 bmcr rw 0x0000 basic mode control register (valid only when mii emulation support is enabled, config1 = 1). 1 bmsr ro 0x0820 basic mode status register (valid only when mii emulation support is enabled, config1 = 1). 2 phyidr1 ro 0x0181 phy identifier register #1 (valid only when mii emulation support is enabled, config1 = 1). 3 phyidr2 ro 0xb900 phy identifier register #2 (valid only when mii emulation support is enabled, config1 = 1). 4 anar ro 0x0021 auto-negotiation advertisement register (valid only when mii emulation support is enabled, config1 = 1). 5 anlpar ro 0x0000 auto-negotiation li nk partner ability register (valid only when mii emulation support is enabled, config1 = 1). 6 aner ro 0x0000 auto-negotiation expansion register (valid only when mii emulation support is enabled, config1 = 1). 7-15 not used tri-state reserved 16 cntrl rw 0x0005 control register 17 status rw 0x0000 status register 18 imask rw 0x0000 interrupt mask register 19 istat rw 0x0000 interrupt status register 20 tx_pcom_hi rw 0x0000 transmit phy communication hi word 21 tx_pcom_lo rw 0x0000 transmit phy communication lo word 22 rx_pcom_hi rw 0x0000 receive phy communication hi word 23 rx_pcom_lo rw 0x0000 receive phy communication lo word 24 peak_noise rw 0xff04 peak level and noise level register 25 noise_cntrl_a rw 0x8007 noise ceiling and noise floor register 26 noise_cntrl_b rw 0x00f4 noise events and noise attack register 27 fwena rw 0x0000 four wire enable and disable link register 28 aid_address rw 0x0000 aid address register 29 aid_cntrl rw 0x4014 aid interval and aid isbi register 30 sym_cntrl rw 0x1c2c data isbi control register 31 tx_sig_cntrl rw 0x4404 transmit pulse control register key to default in the register description that follows, the default column takes the form: , / where : 1 bit set to logic one 0 bit set to logic zero x no default value (pin#) value latched in from pin # at reset : ro = read only rw = read/write : sc = self clearing p = value permanently set ll = latching low lh = latching high
dm9801 1m home phoneline network physical layer single chip transceiver 24 preliminary version: dm9801-ds-p02 march 20, 2000 basic mode control register (bmcr) - register 0 bit bit name default description 0.15 reset 0, rw/sc reset: 1=software reset 0=normal operation when set this bit configures the phy status and control registers to their default states. this bit will return a value of one until the reset process is complete 0.14 loopback 0, rw loopback: loopback control register 1=loopback enabled 0=normal operation 0.13 speed selection 0, ro/p speed select: the dm9801 does not support this function. this bit is permanently set to 0 0.12 auto-negotiation enable 0,ro/p auto-negotiation enable: the dm9801 does not support this function. this bit is permanently set to 0 0.11 power down 0,rw power down: 1=power down enabled 0=normal operation setting this bit will power down the dm9801 with the exception of the crystal oscillator circuit. 0.10 isolate 0,rw isolate: 1= isolate 0= normal operation when this bit is set the data pa th will be isolated from the mii interface. tx_clk, rx_clk, rx_dv, rxd[3:0], col and crs will be placed in a high impedance state. the management interface is not effected by this bit. when the phy address is set to 00000 the isolate bit will be set upon power-up/reset. 0.9 restart auto- negotiation 0,ro/p restart auto-negotiation: the dm9801 does not support this function. this bit is permanently set to 0 0.8 duplex mode 0,ro/p duplex mode: the dm9801 does not support this function. this bit is permanently set to 0 0.7 collision test 0,ro/p collision test: the dm9801 does not support this function. this bit is permanently set to 0 0.6-0.0 reserved 0,ro reserved: write as 0, ignore on read
dm9801 1m home phoneline network physical layer single chip transceiver preliminary 25 version: dm9801-ds-p02 march 20, 2000 basic mode status register (bmsr) - register 1 bit bit name default description 1.15 100base-t4 0,ro/p reserved: the dm9801 does not support this function. this bit is permanently set to 0 1.14 100base-tx full duplex 0,ro/p reserved: the dm9801 does not support this function. this bit is permanently set to 0 1.13 100base-tx half duplex 0,ro/p reserved: the dm9801 does not support this function. this bit is permanently set to 0 1.12 10base-t full duplex 0,ro/p reserved: the dm9801 does not support this function. this bit is permanently set to 0 1.11 10base-t half duplex 1,ro/p reserved: the dm9801 supports half duplex operation only. this bit is permanently set to 1 1.10-1.7 reserved 0,ro reserved: write as 0, ignore on read 1.6 mf preamble suppression 0,ro/p mii frame preamble suppression: 1=phy will accept management frames with preamble suppressed 0=phy will not accept management frames with preamble suppressed 1.5 auto-negotiation complete 1,ro/p auto-negotiation complete: the dm9801 does not support this function. this bit is permanently set to 1 1.4 remote fault 0,ro/p remote fault: the dm9801 does not support this function. this bit is permanently set to 0 1.3 auto-negotiation ability 0,ro/p auto configuration ability: the dm9801 does not support this function. this bit is permanently set to 0 1.2 link status 0,ro/ll link status: 1=valid link established 0=link not established the link status bit is implemented with a latching function, so that the occurrence of a link failure condition causes the link status bit to be cleared and remain cleared until it is read via the management interface 1.1 jabber detect 0,ro/p jabber detect: the dm9801 does not support this function. this bit is permanently set to 0 1.0 extended capability 0,ro/p extended capability: the dm9801 does not support this function. this bit is permanently set to 0 phy id identifier register #1 (phyidr1) - register 2 the phy identifier registers #1 and #2 work together in a si ngle identifier of the dm9801. the identifier consists of a concatenation of the organizationally unique identifier (oui), a vendor's model number, and a model revision number. davicom semiconductor's ieee assigned oui is 00606e.
dm9801 1m home phoneline network physical layer single chip transceiver 26 preliminary version: dm9801-ds-p02 march 20, 2000 bit bit name default description 2.15-2.0 oui_msb <0181h> oui most significant bits: this register stores bits 3 - 18 of the oui (00606e) to bits 15 - 0 of this register respectively. the most significant two bits of the oui are ignored (the ieee standard refers to these as bit 1 and 2) phy identifier register #2 (phyidr2) - register 3 bit bit name default description 3.15-3.10 oui_lsb <101110>,ro/p oui least significant bits: bits 19 - 24 of the oui (00606e) are mapped to bits 15 - 10 of this register respectively 3.9-3.4 vndr_mdl <010000>,ro/p vendor model number: six bits of the vendor model number mapped to bits 9 - 4 (most significant bit to bit 9) 3.3-3.0 mdl_rev <0000>,ro/p model revision number: four bits of the vendor model revision number mapped to bits 3 - 0 (most significant bit to bit 3) auto-negotiation advertisement register(anar) - register 4 this register contains the advertised abilities of the dm9801 devi ce as they will be transmitted to link partners during auto- negotiation. bit bit name default description 4.15 np 0,ro/p next page indication: the dm9801 does not support the next page function. this bit is permanently set to 0 4.14 ack 0,ro/p acknowledge: 1=link partner ability data reception acknowledged 0=not acknowledged the dm9801's state machine will automatically control this bit. software should not attempt to write to this bit. 4.13 rf 0, ro/p remote fault: the dm9801 does not support this function. this bit is permanently set to 0 4.12-4.11 reserved 0, ro reserved: write as 0, ignore on read 4.10 fcs 0, ro/p flow control support: the dm9801 does not support this function. this bit is permanently set to 0 4.9 t4 0, ro/p 100base-t4 support: the dm9801 does not support this function. this bit is permanently set to 0 4.8 tx_fdx 0, ro/p 100base-tx full duplex support: the dm9801 does not support this function. this bit is permanently set to 0 4.7 tx_hdx 0, ro/p 100base-tx support: the dm9801 does not support this function. this bit is permanently set to 0
dm9801 1m home phoneline network physical layer single chip transceiver preliminary 27 version: dm9801-ds-p02 march 20, 2000 auto-negotiation advertisement register(anar) - register 4 (continued) bit bit name default description 4.6 10_fdx 0, ro/p 10base-t full duplex support: the dm9801 does not support this function. this bit is permanently set to 0 4.5 10_hdx 1, ro/p 10base-t support: 1=10base-t half duplex supported by the link partner 0=10base-t half duplex not supported by the link partner 4.4-4.0 selector <00001>, ro/p protocol selection bits: these bits contain the binary encoded protocol selector supported by this node. <00001> indicates that this device supports ieee 802.3 csma/cd. auto-negotiation link partner ability register (anlpar) - register 5 this register contains the advertised abilities of the li nk partner as they are received during auto-negotiation. bit bit name default description 5.15 np 0, ro/p next page indication: 0= link partner, no next page available 1= link partner, next page available 5.14 ack 0, ro/p acknowledge: 1=link partner ability data reception acknowledged 0=not acknowledged the dm9801's state machine will automatically control this bit. software should not attempt to write to this bit. 5.13 rf 0, ro/p remote fault: 1=remote fault indicated by link partner 0=no remote fault indicated by link partner 5.12-5.10 reserved 0, ro reserved: write as 0, ignore on read 5.9 t4 0, ro/p 100base-t4 support: the dm9801 does not support this function. this bit is permanently set to 0 5.8 tx_fdx 0, ro/p 100base-tx full duplex support: the dm9801 does not support this function. this bit is permanently set to 0 5.7 tx_hdx 0, ro/p 100base-tx support: the dm9801 does not support this function. this bit is permanently set to 0 5.6 10_fdx 0, ro/p 10base-t full duplex support: the dm9801 does not support this function. this bit is permanently set to 0 5.5 10_hdx 0, ro 10base-t support: 1=10base-t half duplex supported by the link partner 0=10base-t half duplex not supported by the link partner 5.4-5.0 selector <00000>, ro protocol selection bits: link partner binary encoded protocol selector
dm9801 1m home phoneline network physical layer single chip transceiver 28 preliminary version: dm9801-ds-p02 march 20, 2000 auto-negotiation expansion register (aner) - register 6 bit bit name default description 6.15-6.5 reserved 0, ro reserved: write as 0, ignore on read 6.4 pdf 0, ro/p local device parallel detection fault: pdf=1: a fault detected via parallel detection function. pdf=0: no fault detected via parallel detection function dm9801 does not support this function, so this bit is always 0. 6.3 lp_np_able 0, ro/p link partner next page able: lp_np_able=1: link partner, next page available lp_np_able=0: link partner, no next page dm9801 does not support this function, so this bit is always 0. 6.2 np_able 0,ro/p local device next page able: np_able=1: dm9801, next page available np_able=0: dm9801, no next page dm9801 does not support this function, so this bit is always 0. 6.1 page_rx 0, ro/p new page received: a new link code word page re ceived. this bit will be automatically cleared when the register (register 6) is read by management. dm9801 does not support this function, so this bit is always 0. 6.0 lp_an_able 0, ro/p link partner auto-negotiation able: lp_an_able=1 indicates that the link partner supports auto- negotiation. dm9801 does not support this function, so this bit is always 0. control register - register 16 bit bit name default description 16.15 ig_rmt_cmds 0,rw ignore remote commands: 1=remote commands are ignored 0=remote commands will be accepted from any node in the network. the value of the cmdena pin is latched into this bit at power-up/reset. 16.14 avg_peak_rl 0,rw average peak rule: 1= average peak with measured noise instead of noise + 25% 0= normal operation 16.13 en_short_cd 0,rw enable short cd: 1= enable short cd noise rule do not count bad sync if cd is longer than 160us 0= normal operation 16.12 dis_inc_noise 0,rw disable increment of noise: 1= disable 25% increase of noise slice when in a packet 0= normal operation 16.11 cmd_lo_pwr 0,rw command low power: 1= transmit power is set to low 0= normal operation remote commands will be issued if this bit is set 16.10 cmd_hi_pwr 0,rw command high power: 1= transmit power is set to high 0= normal operation remote commands will be issued if this bit is set
dm9801 1m home phoneline network physical layer single chip transceiver preliminary 29 version: dm9801-ds-p02 march 20, 2000 control register - register 16 (continued) bit bit name default description 16.9 cmd_lo_spd 0,rw command low speed: 1= transmit speed is set to low 0= normal operation remote commands will be issued if this bit is set 16.8 cmd_hi_spd 0,rw command high speed: 1= transmit speed is set to high 0= normal operation remote commands will be issued if this bit is set 16.7 aid_adr_neg 0,rw aid address negotiation: 1= stop aid address negotiation 0= normal operation 16.6 clr_ns_evnt 0,rw clear noise event register: 1= clear the noise event register 0= normal operation 16.5 slc_lvl_adp 0,rw slice level adaptation: 1= slice level adaptation is disabled (stopped). 0= slice level adaptation is enabled 16.4 pwr_dwn 0,rw power down: writing a 1 to this bit will cause dm9801 to enter sleep mode and power down all circuits except the oscillator and clock generator circuit. to exit sleep mode, write 0 to this bit position. the prior configuration will be retained when the sleep state is terminated, but the state machine will be reset 16.3 reserved 0,rw reserved: this bit must be written as 0 16.2 speed 1, rw speed: 1= high speed 0= low speed this bit indicates the network speed is set to high as selected by the status of the spdsel pin during power-up/reset. 16.1 power 0, rw power: 1= high power 0= low power this bit indicates the network power is set to high as selected by the status of the pwrsel pin during power-up/reset. 16.0 reserved 1,rw reserved: this bit must be written as 1
dm9801 1m home phoneline network physical layer single chip transceiver 30 preliminary version: dm9801-ds-p02 march 20, 2000 status register - register 17 bit bit name default description 17.15 ? 17.11 reserved 0, rw reserved: write as 0, ignore on read 17.10 link_sta 0, ro link status: this bit reports the link status of the dm9801 17.9 dis_led_str 0, rw disable led stretchers: this bit disables led pulse stretchers 17.8 ? 17.7 reserved 0, rw reserved: write as 0, ignore on read 17.6 rx_pwr 0, ro receive power: this bit is an indication of the current receive signal power. 1= the receive signal power is high. 0= the receive signal power is low. 17.5 rx_spd 0, ro receive speed: this bit is an indication of the current receive speed. 1= the receive speed is high. 0= the receive speed is low. 17.4 rx_ver 0, ro receive version: this bit is an indication of the current receive version. 1= the receive version is not version 0. 0= the receive version is version 0. 17.3 - 17.0 reserved 0, rw reserved: write as 0, ignore on read imask (interrupt mask) register - register 18 bit bit name default description 18.15 ? 18.10 software interrupts 0,rw software interrupts: 1= software interrupts will not activate the int# pin 0= software interrupts will activate the int# pin 18.9 msk_rx_pcom 0,rw mask rxpcom valid: 1= rx_pcom_val will not activate the int# pin 0= rx_pcom_val will activate the int# pin 18.8 msk_tx_pcom 0,rw mask txpcom ready: 1= tx_pcom_rdy will not activate the int# pin 0= tx_pcom_rdy will activate the int# pin 18.7 ? 18.4 reserved 0,rw reserved: write as 0, ignore on read 18.3 msk_pkt_rcv 0,rw mask packet received: 1= packet received will not activate the int# pin 0= packet received will activate the int# pin 18.2 msk_pkt_xmit 0,rw packet transmitted: 1= packet transmitted will not activate the int# pin 0= packet transmitted will activate the int# pin 18.1 msk_rmt_rcv 0,rw remote command received: 1= remote command received will not activate the int# pin 0= remote command received will activate the int# pin 18.0 msk_cmd_snt 0,rw remote command sent: 1= remote command sent will not activate the int# pin 0= remote command sent will activate the int# pin.
dm9801 1m home phoneline network physical layer single chip transceiver preliminary 31 version: dm9801-ds-p02 march 20, 2000 istat (interrupt status) register - register 19 this register reports the state of each interrupt so urce regardless of the state of the imask register. bit bit name default description 19.15 ? 19.10 software interrupts 0,rw software interrupts: when set any bit of those registers indicates software interrupt is on. 19.9 rx_pcom_val 0,rw rxpcom valid: when set this bit indicates a non-null rx_pcom has been received. accessing the high byte of the rx_pcom register clears this bit. 19.8 tx_pcom_rdy 0,rw txpcom ready: when set this bit indicates a non-null tx_pcom has been loaded into the tx_pcom register. 19.7 ? 19.4 reserved 0,rw reserved: write as 0, ignore on read 19.3 pkt_rcvd 0,rw packet received: when set this bit indicates a packet has been received 19.2 pkt_xmitd 0,rw packet transmitted: when set this bit indicates a packet has been transmitted 19.1 rmt_cmd_rcv 0,rw remote command received: when set this bit indicates a valid remote command has been received. 19.0 rmt_cmd_snt 0,rw remote command sent: when set this bit indicates a valid remote command has been sent. tx_pcom high register - register 20 bit bit name default description 20.15 ? 20.0 tx_pcom_hi 0, rw tx_pcom_hi: the high order word of the 32-bit transmitted data field to be used for out-of-band communications between phy management entities. the phy will send all-0 pcoms un til the high byte has been accessed. an access of any of the four tx_pcom bytes will clear the tx_pcom_rdy bit in the istat register. tx_pcom low register - register 21 bit bit name default description 21.15 ? 21.0 tx_pcom_lo 0, rw tx_pcom_lo: the low order word of the 32-bit transmitted data field to be used for out-of-band communications between phy management entities. the phy will send all-0 pcoms until the high byte in tx_pcom_hi has been accessed. an access of any of the four tx_pcom bytes will clear the tx_pcom_rdy bit in the istat register.
dm9801 1m home phoneline network physical layer single chip transceiver 32 preliminary version: dm9801-ds-p02 march 20, 2000 rx_pcom high register - register 22 bit bit name default description 22.15 ? 22.0 rx_pcom_hi 0, rw rx_pcom_hi: the high order word of the 32-bit receive data field to be used for out- of-band communications between phy management entities. a non-null receive pcom will set the rx_pcom_val bit in the istat register. an access of the high byte of this register will clear the rx_pcom_val bit in the istat register. rx_pcom low register - register 23 bit bit name default description 23.15 ? 23.0 rx_pcom_lo 0, rw rx_pcom_lo: the low order word of the 32-bit receive data field to be used for out-of- band communications between phy management entities. a non-null receive pcom will set the rx_pcom_val bit in the istat register. an access of the high byte of the rx_pcom_hi register will clear the rx_pcom_val bit in the istat register. peak noise register - register 24 bit bit name default description 24.15 - 24.8 peak_level 0xff, rw peak level: this is a measurement of the peak level of the last valid (non-collision) aid received also, the maximum allowable value of the noise measurement. if noise_level exceeds peak_level, noise_level is reset to noise_floor. 24.7 - 24.0 noise_level 0x04, rw noise level: this is the digital value of the slice_lvl_noise output. it is effectively a measure of the noise level on the wire. when auto- adaptation is enabled (bit 5 of the control register is false) this register is updated with the current noise count every 50n secs. when adaptation is disabled, this register can be written and is used to generate both the slice_lvl_noise and the slice_lvl_data signals. noise control a register - register 25 bit bit name default description 25.15 - 25.8 nse_ceiling 0x80, rw noise ceiling: the maximum value of the noise_level measurement. 25.7 - 25.0 nse_floor 0x07, rw noise floor: the minimum value of the noise_level measurement.
dm9801 1m home phoneline network physical layer single chip transceiver preliminary 33 version: dm9801-ds-p02 march 20, 2000 noise control b register - register 26 bit bit name default description 26.15 - 26.8 nse_events 0x00, rw noise events: an 8 bit counter that records the number of noise events detected. overflows are held as 0xff. this register is cleared by setting bit 6 of the control register (clr_ns_evnt). 26.7 - 26.0 nse_attack 0xf4, rw noise attack: sets the attack characteristics of the noise algorithm. the high nibble sets the number of noise events needed to raise the noise_level immediately, while the low nibble is the number of noise events needed to raise the noise_level at the end of an 870 msec period. aid address register - register 27 bit bit name default description 27.15 - 27.2 reserved 0, rw reserved: these bits will always be read as 0. 27.1 dis_lnk 0, rw disable link: this bit disables link integrity feature. 27.0 fwena 0, rw four wire enable: when read this bit will indicate the status of fwena (pin 57) as read during power up. if the fwena pin status is 1 on power up, this bit can be written to change the fwena status. if the fwena pin status is 0 on power up, writes to this bit are ignored. aid address register - register 28 bit bit name default description 28.15 - 28.8 reserved 0x00, rw reserved: these bits will always be read as 0. 28.7 - 28.0 aid_address 0x00, rw aid address: unless bit 7 of the control register is set, the dm9801 is assured to select a unique aid address. addresses above 0xef are reserved. address 0xff is defined to indicate a remote command. aid control register - register 29 bit bit name default description 29.15 - 29.8 aid_isbi 0x40, rw aid inter symbol blanking interval: this value defines the number of tclks (116.7ns) between aid pulses for symbol 0. 29.7 - 29.0 aid_interval 0x14, rw aid interval: this value defines the number of tclks (116.7ns) separating aid symbols.
dm9801 1m home phoneline network physical layer single chip transceiver 34 preliminary version: dm9801-ds-p02 march 20, 2000 symbol control register - register 30 bit bit name default description 30.15 - 30.8 isbi_fast 0x1c, rw inter symbol blanking interval (high speed): this value defines the number of tclks (116.7ns) between data pulses for symbol 0 in high speed 30.7 - 30.0 isbi_slow 0x2c, rw inter symbol blanking interval (low speed): this value defines the number of tclks (116.7ns) between data pulses for symbol 0 in low speed tx signal control register - register 31 bit bit name default description 31.15 - 31.8 tx_pls_cycls 0x44, rw transmit pulse cycles: the low nibble of this register indicates the number of pulses on the hnn pins while the high nibble indicates the number of pulses on the hnp pins. 31.7 - 31.0 tx_pls_width 0x04, rw transmit pulse width: this value determines the duration in osc cycles (16.7 ns) that a transmit pulse lasts.
dm9801 1m home phoneline network physical layer single chip transceiver preliminary 35 version: dm9801-ds-p02 march 20, 2000 spi serial management register map (intfsel = 1, gpsi mode) register address register name access type default value description 1-0 cntrl rw 0x0005 control registers 3-2 status rw 0x0000 status registers 5-4 imask rw 0x0000 interrupt mask registers 7-6 istat rw 0x0000 interrupt status registers 9-8 tx_pcom_lo rw 0x0000 transmit phy communication low word 11-10 tx_pcom_hi rw 0x0000 transmit phy communication high word 13-12 rx_pcom_lo rw 0x0000 receive phy communication low word 15-14 rx_pcom_hi rw 0x0000 receive phy communication high word 19-18 peak_noise rw 0xff04 peak level and noise level registers 17-16 noise_cntrl_a rw 0x8007 noise ceiling and noise floor registers 21-20 noise_cntrl_b rw 0x00f4 noise events and noise attack registers 22 fwena rw 0x00 four wire enable and link disable registers 24-23 reserved reserved 25 aid_address rw 0x00 aid address register 27-26 aid_cntrl rw 0x4014 aid interval and aid isbi registers 29-28 sym_cntrl rw 0x1c2c data isbi control registers 31-30 tx_sig_cntrl rw 0x4404 transmit pulse control registers spi serial management control register - register 0 (intfsel = 1, gpsi mode) bit bit name default description 0.7 aid_adr_neg 0,rw aid address negotiation: 1= stop aid address negotiation 0= normal operation 0.6 clr_ns_evnt 0,rw clear noise event register: 1= clear the noise event register 0= normal operation 0.5 slc_lvl_adp 0,rw slice level adaptation: 1= slice level adaptation is disabled (stopped). 0= slice level adaptation is enabled 0.4 pwr_dwn 0,rw power down: writing a 1 to this bit will cause dm9801 to enter sleep mode and power down all circuits except the oscillator and clock generator circuit. to exit sleep mode, write 0 to this bit position. the prior configuration will be retained when the sleep state is terminated, but the state machine will be reset 0.3 reserved 0,rw reserved: this bit must be written as 0 0.2 speed 1,rw speed: 1= high speed 0= low speed this bit indicates the network speed is set to high as selected by the status of the spdsel pin during power-up/reset. 0.1 power 0,rw power: 1= high power 0= low power this bit indicates the network power is set to high as selected by the status of the pwrsel pin during power-up/reset.
dm9801 1m home phoneline network physical layer single chip transceiver 36 preliminary version: dm9801-ds-p02 march 20, 2000 spi serial management control register - register 0 (continued) (intfsel = 1, gpsi mode) bit bit name default description 0.0 reserved 1,rw reserved: this bit must be written as 1 spi serial management control register - register 1 (intfsel = 1, gpsi mode) bit bit name default description 1.7 ig_rmt_cmds 0,rw ignore remote commands: 1=remote commands are ignored 0=remote commands will be accepted from any node in the network. the value of the cmdena pin is latched into this bit at power-up/reset. 1.6 avg_peak_rl 0,rw average peak rule: 1= average peak with measured noise instead of noise + 25% 0= normal operation 1.5 en_short_cd 0,rw enable short cd: 1= enable short cd noise rule do not count bad sync if cd is longer than 160us 0= normal operation 1.4 dis_inc_noise 0,rw disable increment of noise: 1= disable 25% increase of noise slice when in a packet 0= normal operation 1.3 cmd_lo_pwr 0,rw command low power: 1= transmit power is set to low 0= normal operation remote commands will be issued if this bit is set 1.2 cmd_hi_pwr 0,rw command high power: 1= transmit power is set to high 0= normal operation remote commands will be issued if this bit is set 1.1 cmd_lo_spd 0,rw command low speed: 1= transmit speed is set to low 0= normal operation remote commands will be issued if this bit is set 1.0 cmd_hi_spd 0,rw command high speed: 1= transmit speed is set to high 0= normal operation remote commands will be issued if this bit is set spi serial management status register - register 2 (intfsel = 1, gpsi mode) bit bit name default description 2.7 reserved 0.rw reserved: write as 0, ignore on read 2.6 rx_pwr 0, ro receive power: this bit is an indication of the current receive signal power. 1= the receive signal power is high. 0= the receive signal power is low. 2.5 rx_spd 0, ro receive speed: this bit is an indication of the current receive speed. 1= the receive speed is high. 0= the receive speed is low.
dm9801 1m home phoneline network physical layer single chip transceiver preliminary 37 version: dm9801-ds-p02 march 20, 2000 spi serial management status register - register 2 (continued) (intfsel = 1, gpsi mode) bit bit name default description 2.4 rx_ver 0, ro receive version: this bit is an indication of the current receive version. 1= the receive version is not version 0. 0= the receive version is version 0. 2.3 ? 2.0 reserved 0, rw reserved: write as 0, ignore on read spi serial management status register - register 3 (intfsel = 1, gpsi mode) bit bit name default description 3.7 invrt_crs 0, rw invert crs signal: when this bit is set the crs signal on the dm9801 will be inverted. 3.6 invrt_col 0, rw invert col signal: when this bit is set the col signal on the dm9801 will be inverted. 3.5 invrt_txclk 0, rw invert transmit clock: when this bit is set the tx_clk signal on the dm9801 will be inverted. 3.4 invrt_rxclk 0, rw invert receive clock: when this bit is set the rx_clk signal on the dm9801 will be inverted. 3.3 reserved 0, rw reserved: write as 0, ignore on read 3.2 link_sta 0, ro link status: this bit reports the link status of the dm9801 3.1 dis_led_str 0, rw disable led stretchers: this bit disables led pulse stretchers 3.0 reserved 0, rw reserved: write as 0, ignore on read imaska (interrupt mask a) register - register 4 (intfsel = 1, gpsi mode) bit bit name default description 4.7 ? 4.4 reserved 0,rw reserved: write as 0, ignore on read 4.3 msk_pkt_rcv 0,rw mask packet received: 1= packet received will not activate the int# pin 0= packet received will activate the int# pin 4.2 msk_pkt_xmit 0,rw packet transmitted: 1= packet transmitted will not activate the int# pin 0= packet transmitted will activate the int# pin 4.1 msk_rmt_rcv 0,rw remote command received: 1= remote command received will not activate the int# pin 0= remote command received will activate the int# pin 4.0 msk_cmd_snt 0,rw remote command sent: 1= remote command sent will not activate the int# pin 0= remote command sent will activate the int# pin.
dm9801 1m home phoneline network physical layer single chip transceiver 38 preliminary version: dm9801-ds-p02 march 20, 2000 imaskb (interrupt mask b) register - register 5 (intfsel = 1, gpsi mode) bit bit name default description 5.7 ? 5.2 software interrupts 0,rw software interrupts: 1= software interrupts will not activate the int# pin 0= software interrupts will activate the int# pin 5.1 msk_rx_pcom 0,rw mask rxpcom valid: 1= rx_pcom_val will not activate the int# pin 0= rx_pcom_val will activate the int# pin 5.0 msk_tx_pcom 0,rw mask txpcom ready: 1= tx_pcom_rdy will not activate the int# pin 0= tx_pcom_rdy will ac tivate the int# pin istat (interrupt status a) register - register 6 (intfsel = 1, gpsi mode) this register reports the state of each interrupt so urce regardless of the state of the imask register. bit bit name default description 6.7 ? 6.4 reserved 0,rw reserved: write as 0, ignore on read 6.3 pkt_rcvd 0,rw packet received: when set this bit indicates a packet has been received 6.2 pkt_xmitd 0,rw packet transmitted: when set this bit indicates a packet has been transmitted 6.1 rmt_cmd_rcv 0,rw remote command received: when set this bit indicates a valid remote command has been received. 6.0 rmt_cmd_snt 0,rw remote command sent: when set this bit indicates a valid remote command has been sent. istat (interrupt status b) register - register 7 (intfsel = 1, gpsi mode) this register reports the state of each interrupt so urce regardless of the state of the imask register. bit bit name default description 7.7 ? 7.2 software interrupts 0,rw software interrupts: when set any bit of those registers indicates software interrupt is on. 7.1 rx_pcom_val 0,rw rxpcom valid: when set this bit indicates a non-null rx_pcom has been received. accessing the high byte of the rx_pcom register clears this bit. 7.0 tx_pcom_rdy 0,rw txpcom ready: when set this bit indicates a non-null tx_pcom has been loaded into the tx_pcom register.
dm9801 1m home phoneline network physical layer single chip transceiver preliminary 39 version: dm9801-ds-p02 march 20, 2000 tx_pcom low b register - register 8 (intfsel = 1, gpsi mode) bit bit name default description 8.7 ? 8.0 tx_pcom_lob 0, rw tx_pcom_lob: the 7 th through the lsb of the 32-bit transmitted data field to be used for out-of-band communications between phy management entities. the phy will send all-0 pcoms until the high byte in tx_pcom_hi has been accessed. an access of any of the four tx_pcom bytes will clear the tx_pcom_rdy bit in the istat register. tx_pcom low a register - register 9 (intfsel = 1, gpsi mode) bit bit name default description 9.7 ? 9.0 tx_pcom_loa 0, rw tx_pcom_loa: the 15 th through 8 th bits of the 32-bit transmitted data field to be used for out-of-band communications between phy management entities. the phy will send all-0 pcoms until the high byte in tx_pcom_hi has been accessed. an access of any of the four tx_pcom bytes will clear the tx_pcom_rdy bit in the istat register. tx_pcom high b register - register 10 (intfsel = 1, gpsi mode) bit bit name default description 10.7 ? 10.0 tx_pcom_hib 0, rw tx_pcom_hib: the 23 rd through the 16 th bits transmitted data field to be used for out- of-band communications between phy management entities. the phy will send all-0 pcoms un til the high byte has been accessed. an access of any of the four tx_pcom bytes will clear the tx_pcom_rdy bit in the istat register. tx_pcom high a register - register 11 (intfsel = 1, gpsi mode) bit bit name default description 11.7 ? 11.0 tx_pcom_hia 0, rw tx_pcom_hia: the msb of the 32-bit transmitted data field to be used for out-of-band communications between phy management entities. the phy will send all-0 pcoms un til the high byte has been accessed. an access of any of the four tx_pcom bytes will clear the tx_pcom_rdy bit in the istat register. rx_pcom low b register - register 12 (intfsel = 1, gpsi mode) bit bit name default description 12.7 ? 12.0 rx_pcom_lob 0, rw rx_pcom_lob: the lsb of the 32-bit receive data field to be used for out-of-band communications between phy management entities. a non-null receive pcom will set the rx_pcom_val bit in the istat register. an access of the high byte of the rx_pcom_hi register will clear the rx_pcom_val bit in the istat register.
dm9801 1m home phoneline network physical layer single chip transceiver 40 preliminary version: dm9801-ds-p02 march 20, 2000 rx_pcom low a register - register 13 (intfsel = 1, gpsi mode) bit bit name default description 13.7 ? 13.0 rx_pcom_loa 0, rw rx_pcom_loa: the 15 th through the 8 th bits of the 32-bit receive data field to be used for out-of-band communications between phy management entities. a non-null receive pcom will set the rx_pcom_val bit in the istat register. an access of the high byte of the rx_pcom_hi register will clear the rx_pcom_val bit in the istat register. rx_pcom high b register - register 14 (intfsel = 1, gpsi mode) bit bit name default description 14.7 ? 14.0 rx_pcom_hib 0, rw rx_pcom_hib: the 23 rd through the 16 th bits of the 32-bit receive data field to be used for out-of-band communications between phy management entities. a non-null receive pcom will set the rx_pcom_val bit in the istat register. an access of the high byte of this register will clear the rx_pcom_val bit in the istat register. rx_pcom high a register - register 15 (intfsel = 1, gpsi mode) bit bit name default description 15.7 - 15.0 rx_pcom_hia 0, rw rx_pcom_hia: the msb of the 32-bit receive data field to be used for out-of-band communications between phy management entities. a non-null receive pcom will set the rx_pcom_val bit in the istat register. an access of the high byte of this register will clear the rx_pcom_val bit in the istat register. noise level register - register 16 (intfsel = 1, gpsi mode) bit bit name default description 16.7 - 16.0 noise_level 0x04, rw noise level: this is the digital value of the slice_lvl_noise output. it is effectively a measure of the noise level on the wire. when auto- adaptation is enabled (bit 5 of the control register is false) this register is updated with the current noise count every 50n secs. when adaptation is disabled, this register can be written and is used to generate both the slice_lvl_noise and the slice_lvl_data signals. peak level register - register 17 (intfsel = 1, gpsi mode) bit bit name default description 17.7 - 17.0 peak_level 0xff, rw peak level: this is a measurement of the peak level of the last valid (non-collision) aid received also, the maximum allowable value of the noise measurement. if noise_level exceeds peak_level, noise_level is reset to noise_floor.
dm9801 1m home phoneline network physical layer single chip transceiver preliminary 41 version: dm9801-ds-p02 march 20, 2000 noise floor register - register 18 (intfsel = 1, gpsi mode) bit bit name default description 18.7 - 18.0 nse_floor 0x07, rw noise floor: the minimum value of the noise_level measurement. noise ceiling register - register 19 (intfsel = 1, gpsi mode) bit bit name default description 19.7 - 19.0 nse_ceiling 0x80, rw noise ceiling: the maximum value of the noise_level measurement. noise attack register - register 20 (intfsel = 1, gpsi mode) bit bit name default description 20.7 - 20.0 nse_attack 0xf4, rw noise attack: sets the attack characteristics of the noise algorithm. the high nibble sets the number of noise events needed to raise the noise_level immediately, while the low nibble is the number of noise events needed to raise the noise_level at the end of an 870 msec period. noise events register - register 21 (intfsel = 1, gpsi mode) bit bit name default description 21.7 - 21.0 nse_events 0x00, rw noise events: an 8 bit counter that records the number of noise events detected. overflows are held as 0xff. this register is cleared by setting bit 6 of the control register (clr_ns_evnt). four wire enable register - register 22 (intfsel = 1, gpsi mode) bit bit name default description 22.7 - 22.2 reserved 0, rw reserved these bits will always be read as 0. 22.1 dis_lnk 0, rw disable link: this bit disables link integrity feature. 22.0 fwena 0, rw four wire enable: when read this bit will indicate the status of fwena (pin 57) as read during power up. if the fwena pin status is 1 on power up, this bit can be written to change the fwena status. if the fwena pin status is 0, on power up, writes to this bit are ignored. aid address register - register 25 (intfsel = 1, gpsi mode) bit bit name default description 25.7 - 25.0 aid_address 0x00, rw aid address: unless bit 7 of the control register is set, the dm9801 is assured to select a unique aid address. addresses above 0xef are reserved. address 0xff is defined to indicate a remote command.
dm9801 1m home phoneline network physical layer single chip transceiver 42 preliminary version: dm9801-ds-p02 march 20, 2000 aid interval register - register 26 (intfsel = 1, gpsi mode) bit bit name default description 26.7 - 26.0 aid_interval 0x14, rw aid interval: this value defines the number of tclks (116.7ns) separating aid symbols. aid inter-symbol blanking interval register - register 27 (intfsel = 1, gpsi mode) bit bit name default description 27.7 - 27.0 aid_isbi 0x40, rw aid inter symbol blanking interval: this value defines the number of tclks (116.7ns) between aid pulses for symbol 0. isbi slow register - register 28 (intfsel = 1, gpsi mode) bit bit name default description 28.7 - 28.0 isbi_slow 0x2c, rw inter symbol blanking interval (low speed): this value defines the number of tclks (116.7ns) between data pulses for symbol 0 in low speed isbi fast register - register 29 (intfsel = 1, gpsi mode) bit bit name default description 29.7 - 29.0 isbi_fast 0x1c, rw inter symbol blanking interval (high speed): this value defines the number of tclks (116.7ns) between data pulses for symbol 0 in high speed tx pulse width register - register 30 (intfsel = 1, gpsi mode) bit bit name default description 30.7 - 30.0 tx_pls_width 0x04, rw transmit pulse width: this value determines the duration in osc cycles (16.7 ns) that a transmit pulse lasts. tx pulse cycles register - register 31 (intfsel = 1, gpsi mode) bit bit name default description 31.7 - 31.0 tx_pls_cycls 0x44, rw transmit pulse cycles: the low nibble of this register indicates the number of pulses on the hnn pins while the high nibble indicates the number of pulses on the hnp pins.
dm9801 1m home phoneline network physical layer single chip transceiver preliminary 43 version: dm9801-ds-p02 march 20, 2000 1 mbps home phoneline network phy the integrated dm9801 transceiver is a physical layer device supporting home phoneline networking. it provides all of the phy layer functions required to support 1 mbps data transfers over existing residential phone wiring. all data bits are encoded into the relative time position of a pulse with respect to the previous one. the wave-form on the wire consists of a 7.5 mhz carrier sinusoid enclosed within an exponential (bell shaped) envelope. the waveform is produced by generating four 7.5 mhz square wave cycles and passing them through an external bandpass filter. the home phoneline network phy frame consists of a home phoneline network header that replaces the normal ethernet 64-bit preamble and delimiter. the frame header is prepended to a standard ethernet packet starting with the destination address and ending with the crc. only the phy layer and its parameters are modified from that of the standard ethernet implementation. the home phoneline network phy layer is designed to operate with a standard ethernet mac layer controller implementing all the csma/cd protocol features. the frame begins with a characteristic sync interval that delineates the beginning of a home phoneline network frame followed by an access id (aid) which encodes 8 bits of aid and 4 bits of control word. the aid is used to detect collisions and is dynamically assigned, while the control word carries speed and power information. the aid is followed by a silence interval, then 32 bits of data reserved for phy layer communication. these bits are accessible via internal registers and are for future use. data encoding consists of two symbol types: an aid symbol and a data symbol. the aid symbol is always transmitted at the same speed and encodes 2 bits that determine the pulse position (one of four) relative to the previous pulse. these bits are transmitted lsb first. the access symbol interval is fixed. the data symbol interval is variable. the arriving bit stream is blocked into from 3-bit to 6-bit blocks according to a proprietary (rll25) algorithm. the bits in each block are then used to encode a data symbol. each symbol consists of a data inter symbol blanking interval (disbi) and then a pulse at one of 25 possible positions. the pulse position and polarity within the interval is determined by the bits in the data block. immediately after the pulse a new symbol interval begins. during the disbi the receiver ignores all incoming pulses to allow network reflections to die out. any station may be programmed to assume the role of a phy master and remotely command, via the control word, the rest of the units on the network to change their transmit speed or power level. many of the framing parameters are programmable in the home phoneline network phy and will allow modifications to transmission speed center frequency as well as noise and reflection rejection algorithms. two default speeds are provided, low at 0.7 mbps and high at 1 mbps. home phoneline network phy medium interface framing the home phoneline network frame on the phone wire network consists of a header generated in the phy prepended to an ieee 802.3 ethernet data packet received from the mac layer. when transmitting on the wire pair, the dm9801 first receives an ethernet mac frame from the mac. the 8 octets of preamble and delimiter are stripped off and replaced with the home phoneline network phy header, then transmitted on the home network with the lsb of each symbol being transmitted first. during a receive operation, the reverse process is executed. when a home phoneline network phy frame is received by the dm9801, the header is stripped off and replaced with the 4 octets of preamble and delimiter of the ieee 802.3 ethernet mac frame specification and then passed on to the mac layer.
dm9801 1m home phoneline network physical layer single chip transceiver 44 preliminary version: dm9801-ds-p02 march 20, 2000 dm9801 1m framing figure 21 dm9801 symbol waveform all dm9801 symbols are composed at the transmitter of a silence interval and a pulse formed of an integer number of cycles (cycles_per_pulse) of a frequency square wave (center_frequency) that has been filtered with a bandpass filter. data is encoded in the same time interval from the preceding pulse. the dm9801 pulse parameters are shown below. parameter value tolerance unit center_frequency 7.5 500 ppm mhz cycles_per_pulse 4 cycle dm9801 1m time intervals are expressed in tine interval clock (tic) units. one tic is defined as 7/(60e6) seconds or approximately 116.67 nano-seconds (ns). access id intervals the dm9801 1m frame begins with an access id interval which is composed of eight equally spaced subintervals termed aid symbols 0 through 7. (refer to figure 21 above) an access id symbol is 129 tics long. transmit timing is shown in figure 22 below. timing starts at the beginning of each aid symbol and ends at tic = 129.
dm9801 1m home phoneline network physical layer single chip transceiver preliminary 45 version: dm9801-ds-p02 march 20, 2000 aid symbol transmit timing figure 22 aid symbol receive timing figure 23
dm9801 1m home phoneline network physical layer single chip transceiver 46 preliminary version: dm9801-ds-p02 march 20, 2000 sync transmit timing the sync interval (aid symbol 0) delineates the beginning of a frame and is composed of a sync_start pulse followed by a sync_end pulse after a fixed silence interval as shown in figure 22 above. timing for this (aid symbol 0) starts (tic = 0) at the beginning of the sync_start pulse. the sync_end pulse starts at tic = 126. at tic = 129, this aid symbol 0 ends and the next aid symbol begins with the symbol timing reference reset to tic = 0. no information bits are coded in the sync (aid symbol 0 interval). sync receive timing as soon as the sync_start pulse is detected, the receiver disables (blanks) further detection until aid_end_blank (located at tic = 61) after which detection is re-enabled for the next received pulse. the receiver allows for jitter by establishing a window around each legal pulse position. this window aid_guard_interval is 2 tics wide on either side of the position. a sync_end pulse which arrives outside aid_guard_interval of the legal tic = 126 is considered a noise_event that may be used in setting the adaptive squelch level, aborts the packet, and sets the receiver in search of a new sync_start pulse and sync interval. if it is a transmitting station, the collision event is asserted. the sync interval is followed by six access id symbols (symbols 1 through6). transmit timing is shown in figure 22 and receive timing in figure 23(above). data is encoded in the relative position of each pulse with respect to the previous one. a pulse may occur at one and only one of the four possible positions within the aid symbol yielding two bits of data coded per aid symbol. the decoded bits from the aid symbols 1 to 4 produce 8 bits of access id which are used to identify individual stations and to detect collisions. the msb is encoded in aid symbol 1 and is the leftmost bit in table 2. pulse position tics from beginning of aid symbol bit encoding 1 66 00 2 86 01 3 106 10 4 126 11 access id symbol pulse position and encoding table 2 the next two aid symbols (5 and 6) encode four bits of control information. the msb is encoded in aid symbol 5. collisions a collision is detected only during access id and silent intervals (aid symbols 0 through 7). in general during a collision a transmitting station will read back an aid value that does not match its own and recognizes the event as a collision alerting other stations with a jam signal. non- transmitting stations may also detect non-conforming aid pulses as collisions. with two transmitters colliding, each transmitter normally blanks its receive input immediately after transmitting and simultaneously receiving a pulse. therefore, only when a transmitting station receives pulses in a position earlier than the position it transmitted will it recognize it as a pulse transmitted by another station and signal a collision. for this reason guaranteed collision is possible only as long as the spacing between successive possible pulse positions in an aid symbol (20 tics or 2.3 s) is greater than the round trip delay between the colliding nodes. at approximately 1.5 ns propagation delay per foot, the maximum distance between two stations must not be greater than 500 feet for collision detection purposes (1.5 s round trip delay plus margin). the following criteria must be met to guarantee reliable collision detection: at least one station of a colliding group must always detect a collision when the delay between the beginning of its transmitted packed and the beginning of the received colliding packed is between -1.5 s and +1.5 s
dm9801 1m home phoneline network physical layer single chip transceiver preliminary 47 version: dm9801-ds-p02 march 20, 2000 collisions (continued) in general, any received pulse at a station that does not conform to the pulse position requirements of aid symbols 0 through 7 shall indicate a collision on the wire. when a transmitting station senses a collision, it emits a jam signal to alert all other stations to the collision. the following conditions signify a collision event: 1. a station receives an aid that does not match the one being sent. 2. a station receives a pulse outside of the aid_guard_interval in aid intervals 0 to 7. 3. a station receives a pulse inside the silent_interval (aid symbol 7). as in all cases, pulses received inside the blanking interval are ignored. passive stations (stations not actively transmitting during the collision) cannot reliably detect collisions. therefore, once a collision is detected by a transmitting station, the station must inform the rest of the stations of the collision with a jam pattern. only a transmitting station emits a jam signal. once a collision is detected, the collision signal to the mac interface is asserted and is not reset until the mac deactivates the tx_en signal and crs is inactive. jam signal a jam pattern consists of one pulse every 32 tics and continues until at least the end of the aid intervals. after the aid intervals, the jam pattern is continued until tx_en from the mac is deactivated. access id values the access id values for slave stations must be picked by each individual station randomly from a set a aid slave numbers. during operation each station monitors the frames received on the wire. if it detects another station using the same aid, it must randomly select a new aid. silence interval (aid symbol 7) the access id symbols are followed by a fixed silence_interval on 129 tics. the receive blanking interval is the same as that of the aid symbols (1 through 6). any pulses detected in the silence_interval are considered as collision event and are handled as described in the collisions section. data symbols data symbols are less robust than access id symbols and do not allow collision detectio n. however, they encode data for a much higher transmission rate. data transmit timing data transmission begins with the beginning of a transmission of a pulse as shown in figure 24 below. transmit timing in tics is measured from this point (tic = 0). depending on the data code, the next pulse may begin at any pulse_position_n, where n = 0 to 24. each position is separated from the previous one by one tic. pulse_position_0 occurs at a value defined in table 3 below. this value determines the transmission speed. when a pulse begins transmission, the previous symbol interval ends and a new one immediately begins. speed setting nominal data rate pulse_position_0 value (in tics) low_speed 0.7 mb/s 44 high_speed 1.0 mb/s 28 blanking interval speed settings table 3 transmit data symbol timing figure 24
dm9801 1m home phoneline network physical layer single chip transceiver 48 preliminary version: dm9801-ds-p02 march 20, 2000 data receive timing the incoming waveform is formed from the transmitted pulse along with any distortions and reflections that occur in the wiring network. the receiver detects the point at which the envelope of the received waveform crosses a set threshold as described in the receiver functions section. immediately after the receive threshold crossing, the receiver disables any further detection for a period of end_data_blank = pulse_position_0 - (minus) 3 tics, starting with the detection of the pulse peak. the receiver is then re-enabled for pulse detection and, upon reception of the next pulse measures the elapsed time (rx_pulse_interval) from the previous pulse. the value is then placed in the nearest pulse position bin (one of 25), where pulse position 0 is at pulse_position_0, and each subsequent position is spaced 1 tic from the previous one as defined in the data transmit timing section. data symbols are therefore variable and depend on the encoded data. receive symbol timing figure 25
dm9801 1m home phoneline network physical layer single chip transceiver preliminary 49 version: dm9801-ds-p02 march 20, 2000 data symbol rll25 encoding the run length limit (rll25)code was developed for the home networking phy. it produces highest bit rate for a given value of isbi (inter-symbol blanking interval) and tic size. in a manor similar to run length limited disk coding, rll27 encodes data bits in groups of various sizes, specifically, 3, 4, 5, and 6 bits. pulse positions are assigned to the encoded bit groups in a manor that causes more data bits to be encoded in positions that ate farther apart. this keeps both the average and minimum bit rates higher. rll25 codes data by traversing a tree as shown in figure 26 below. assuming that successive data bits to be encoded are labeled a, b, c, d?,etc. the encoding process begins at the root node and proceeds as follows: ? if the first bit (bit a) is a one, the next 3 bits (b, c, and d) select which one of the eight positions (1-8) is transmitted. the encoding process then continues at the root node. ? if bit a is a zero and bit b is a one, the next 3 bits (c, d, and e) select which one of eight positions (9-16) is transmitted. the encoding process then continues at the root node. ? if bit a is a zero, bit b is a zero, and bit c is a one, the next 3 bits (d, e, and f) select which one of eight positions (17-24) is transmitted. the encoding process then continues at the root node. ? finally, if bits a, b, and c are all zeros, position 0 is transmitted. the encoding process then continues at the root node. as a result, symbol 0 encodes the 3-bit data pattern 000, positions 1-8 encode the 4-bit data pattern 1bcd, positions 9-16 encode the 5-bit data pattern 01cde, and positions 17-24 encode the 6-bit data pattern 001def. if the data encoded is random, 50% of the positions used will be for 4-bit data patterns, 25% will be for 5-bit data patterns, 12.5% will be for 6-bit data patterns, and 12.5% will be for 3-bit data patterns. rll 25 coding tree figure 26
dm9801 1m home phoneline network physical layer single chip transceiver 50 preliminary version: dm9801-ds-p02 march 20, 2000 management interfaces the dm9801 may be managed from either of two interfaces with managed parameters varying depending on the interface: 1. remote control-word management commands embedded in the aid header on the wire network. 2. management messages from the local management entity. aid header remote control-word commands home phoneline networking stations may be configured either as master stations or slave stations. only one master may exist on a given home phoneline network over which the header is preserved. operation is master station mode is optional while operation is slave mode is a requirement. the master station may send commands embedded in the header control word to remotely set various parameters of the remote slave stations. stations are identified via the aid as follows: 1. the master station is identified on the home phoneline network with an aid of 0xff (hex). 2. the slave is identified with an aid of 0x00 (hex) to 0xef (hex). 3. aid values of 0xf0 to 0xfe are reserved for future use. once a command has been transmitted, the master station must revert to a slave aid so that subsequent control words are not interpreted by the slave stations as new commands. a master remote command must consist of three frames with an aid header of 0xff (hex). since the header is appended (piggy-backed) to packets received from the mac that are normally transmitted independently of the dm9801, master control frames are transmitted only when the mac sends packets to the dm9801. therefore, packets from the master station may be separated by long intervals during which other (slave) stations may transmit their frames. a remote master control-word command must be recognized and executed by a home phoneline networking phy when it receives three consecutive valid frames with an aid of 0xff (hex). valid commands are as follows: 1. set_version - commands slave devices to operate according to 1m home networking version. 2. set_power - commands slave stations to set their transmit level to a prescribed level until another master command is received. 3. set_speed - commands slave stations to set their transmit speed to a prescribed value until another master command is received. the control word bit encoding and possible values are described in table 4 below. bit # indicated status 0 0 = this station is version 0 1 = this station is not version 0 1 0 = frame transmitted at low power 1 = frame transmitted at high power 2 0 = frame transmitted at low speed 0 = frame transmitted at high speed 3 reserved master/slave station control word functions table 4 note: master and slave control word bit encoding are identical.
dm9801 1m home phoneline network physical layer single chip transceiver preliminary 51 version: dm9801-ds-p02 march 20, 2000 absolute maximum ratings* symbol parameter min. max. unit conditions dvcc,avcc supply voltage -0.3 3.6 v vin dc input voltage (vin) -0.5 5.5 v vout dc output voltage(vout) -0.3 3.6 v t a ambient temperature range 0 70 c tc case temperature range 0 85 c @ t a = 70 c tstg storage temperature rang (tstg) -40 +125 c pd power dissipation (pd) --- 0.43 w lt lead temp. (tl, soldering, 10 sec.) --- 235 c esd esd rating (rzap=1.5k,czap=100pf) --- 2000 v comments stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. power consumption: symbol parameter min. max. unit conditions high power, 2 drivers 125 m a 3.3v high power, 1 driver 70 m a 3.3v low power, 2 drivers 70 m a 3.3v pd low power, 1 driver 45 m a 3.3v dc electrical characteristics (vcc = 3.3vdc, 5%, t a =25 c, unless specified otherwise) symbol parameter min. typ. max. unit conditions ttl inputs v il input low voltage 0.8 v i il = -400u a v ih input high voltage 2.0 v i ih = 100u a i il input low current 10 u a v in = 0.4v i ih input high current -10 u a v in = 2.7v mii/gpsi ttl outputs v ol output low voltage 0.4 v i ol = 4m a v oh output high voltage 2.4 v i oh = -4m a led outputs v ol output low voltage 0.4 v i ol = 1m a v oh output high voltage 2.4 v i oh = -0.1m a
dm9801 1m home phoneline network physical layer single chip transceiver 52 preliminary version: dm9801-ds-p02 march 20, 2000 ac electrical characteristics (over full range of operating condition unless specified otherwise) analog transmitter timing diagram hn+/- tpw tpwl tpwh symbol parameter min. typ. max. unit conditions transmitter (analog) t pw pulse width 133 ns t pwh pulse width high 67 ns t pwl pulse width low 67 ns t pwh osc pulse width high 25 ns t pwl osc pulse width low 25 ns mii (media-independent interface) clock timing idle (excluding ifg time) t pwh tx_clk/rx_clk pulse width high 1168 ns t pwl tx_clk/rx_clk pulse width low 1165 ns preamble (first 64 bits of tx mac frame) t tpwh tx_clk pulse width high 468 ns t tpwl tx_clk pulse width low 466 ns t rpwh rx_clk pulse width high - ns t rpwl rx_clk pulse width low - ns data (throughout the data phase) t pwh tx_clk/rx_clk pulse width high 468 ns 3us 5.6us t pwl tx_clk/rx_clk pulse width low 466 ns 3us 23us ifg (88 bit times following crs falling edge) t pwh tx_clk/rx_clk pulse width high 468 ns t pwl tx_clk/rx_clk pulse width low 466 ns notes: 1) during aid interval, rx_clk and tx_clk stop for up to 140 us. 2) during preamble state, rx_clk stays at low.
dm9801 1m home phoneline network physical layer single chip transceiver preliminary 53 version: dm9801-ds-p02 march 20, 2000 mii-1m nibble transmit timing diagram tx_clk t tx h t 2 t tx s t 1 t tx pd txd [0:3], tx_en, tx_er crs hn+/- mii-1m nibble transmit timing parameters symbol parameter min. typ. max. unit conditions t tx s txd[0:3], tx_en, tx_er setup to tx_clk high 10 ns t tx h txd[0:3], tx_en, tx_er hold from tx_clk high 10 ns t 1 tx_en sampled to crs asserted 1.3 us t 2 tx_en sampled to crs de- asserted 36.1 us t tx pd tx_en sampled to hn +/- out (tx latency) 1.3 us mii-1m receive nibble timing diagram rx_clk t 2 t 1 t tx pd rxd [0:3], rx_dv, rx_er crs hn+/- t rx s t rx h t 4 t 3
dm9801 1m home phoneline network physical layer single chip transceiver 54 preliminary version: dm9801-ds-p02 march 20, 2000 mii-1m receive nibble timing parameters symbol parameter min. typ. max. unit conditions t rx s rxd[0:3), rx_dv, rx_er setup to rx_clk high 10 ns t rx h rxd[0:3], rx_dv, rx_er hold from rx_clk high 10 ns t rx pd hn +/- in to rxd[0:3] out (rx latency) 154 us t 1 crs asserted to rxd[0:3], rx_dv, rx_er 153 us t 2 crs de-asserted to rxd[0:3], rx_dv, rx_er 0 ns t 3 hn +/- in to crs asserted 474 ns t 4 hn +/- quiet to crs de-asserted 20.1 us gpsi-1m clock timing parameters symbol parameter min. typ. max. unit conditions gpsi (general purpose serial interface) idle (excluding ifg time) t pwh stdclk/srdclk pulse width high 468 ns t pwl stdclk/srdclk pulse width low 115.3 ns preamble (first 64 bits of tx mac frame) t tpwh stdclk pulse width high 118 ns t tpwl stdclk pulse width low 115.3 ns t rpwh srdclk pulse width high - ns t rpwl srdclk pulse width low - ns data (throughout the data phase) t pwh stdclk/srdclk pulse width high 115.3 ns 8.17 us t pwl stdclk/srdclk pulse width low 115.3 115.3 ns ifg (96 bit times following crs falling edge) t pwh stdclk/srdclk pulse width high 118 ns t pwl stdclk/srdclk pulse width low 115.3 ns notes: 1) during aid interval, srdclk and stdclk stop for up to 140 us. 2) during preamble state, srdclk stays at low.
dm9801 1m home phoneline network physical layer single chip transceiver preliminary 55 version: dm9801-ds-p02 march 20, 2000 gpsi-1m transmit timing diagram stdclk t tx h t 2 t tx s t 1 t tx pd stxdat stxen crs hn+/- gpsi-1m transmit timing parameters symbol parameter min. typ. max. unit conditions t tx s stxdata stxen, setup to stdclk high 10 ns t tx h stxdat, stxen, hold from stdclk high 10 ns t 1 stxen sampled to crs asserted 810 ns t 2 stxen sampled to crs de- asserted 33.83 43.16 us t tx pd stxen sampled to hn +/- out (tx latency) 819.3 ns gpsi-1m receive timing diagram srdclk t 2 t 1 t tx pd srxdat crs hn+/- t rx s t rx h t 4 t 3
dm9801 1m home phoneline network physical layer single chip transceiver 56 preliminary version: dm9801-ds-p02 march 20, 2000 gpsi-1m receive timing parameters symbol parameter min. typ. max. unit conditions t rx s srxdat setup to srdclk high 10 ns t rx h srxdat hold from srdclk high 10 ns t rx pd hn +/- in to srxdat out (rx latency) 143.8 us t 1 crs asserted to srxdat 142.3 us t 2 crs de-asserted to srxdat 233 ns t 3 hn +/- in to crs asserted 458.5 ns t 4 hn +/- quiet to crs de-asserted 17.7 us mdio timing when output by sta mdc t 1 mdio 10ns (min) t 2 10ns (min) mdio timing when output by dm9801 mdc t 3 mdio 0 - 300 ns mii timing parameters symbol parameter min. typ. max. unit conditions t 1 mdio setup before mdc 10 - - ns when output by sta t 2 mdio hold after mdc 10 - - ns when output by sta t 3 mdc to mdio output delay 0 - 100 ns when outptu by dm9801
dm9801 1m home phoneline network physical layer single chip transceiver preliminary 57 version: dm9801-ds-p02 march 20, 2000 spi master mode timing diagram sclk so scs# si b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 tdlyscs l tdlysov twidthclk h twidthclk l tsetsi v instruction byte address byte data byte 0 b7 b6 spi master timing parameters symbol parameter min. typ. max. unit conditions twidthclkh positive half-cycle pulse width 790 810 ns twidthclkl negative half-cycle pulse width 790 810 ns tdlyscsl falling clock edge to scs# low 40 ns tdlysov falling clock edge to so valid 40 60 ns tsetsiv si valid to rising clock edge 20 ns spi slave mode timing diagram sclk si scs# so tsetscsl tsetsiv twidthclk h twidthclkl b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 tdlysov tdlysoz tsetscsh instruction byte address byte data byte (high-z when writing) (don't care on read) data byte spi master timing parameters symbol parameter min. typ. max. unit conditions twidthclkh positive half-cycle pulse width 400 ns twidthclkl negative half-cycle pulse width 400 ns tsetscsl scs# low to rising clock edge 50 ns tsetscsh scs# high to rising edge clock 50 ns tdlysov falling edge clock to so valid 50 ns tdlysoz falling edge clock to so tri-state 100 ns tsetsiv si valid to rising clock edge 50 ns
dm9801 1m home phoneline network physical layer single chip transceiver 58 preliminary version: dm9801-ds-p02 march 20, 2000 magnetics selection guide the dm9801 requires an external bandpass filter to interface to the telephone line. manufacturer part number pulse b6003 delta lanf7309 table 5
dm9801 1m home phoneline network physical layer single chip transceiver preliminary 59 version: dm9801-ds-p02 march 20, 2000 crystal selection guide a crystal can be used to generate figure 27 crystal circuit diagram x1 x2 20mhz crystal 18p cap 18p cap
dm9801 1m home phoneline network physical layer single chip transceiver 60 preliminary version: dm9801-ds-p02 march 20, 2000 package information lqfp 100l outline dimensions unit: inches/mm - ( % _ _ _ - %fubjm' d " " " 4fbujoh1mbof ( % 4ff%fubjm' ) % % & ) & ' d y c f symbol dimensions in inches dimensions in mm a 0.063 max. 1.60 max. a 1 0.004 0.002 0.1 0.05 a 2 0.055 0.002 1.40 0.05 b 0.009 0.002 0.22 0.05 c 0.006 0.002 0.15 0.05 d 0.551 0.005 14.00 0.13 e 0.551 0.005 14.00 0.13 e 0.020 bsc. 0.50 bsc. f 0.481 nom. 12.22 nom. g d 0.606 nom. 15.40 nom. h d 0.630 0.006 16.00 0.15 h e 0.630 0.006 16.00 0.15 l 0.024 0.006 0.60 0.15 l 1 0.039 ref. 1.00 ref. y 0.004 max. 0.1 max. 0 ~ 12 0 ~ 12 notes: 1. dimension d & e do not include resin fins. 2. dimension gd is for pc board surface mount pad pitch design reference only. 3. all dimensions are based on metric system.
dm9801 1m home phoneline network physical layer single chip transceiver preliminary 61 version: dm9801-ds-p02 march 20, 2000 ordering information part number pin count package DM9801E 100 lqfp disclaimer the information appearing in this publication is believed to be accurate. integrated circuits sold by davicom semiconductor are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. davicom makes no warranty, express, statutory, implied or by description rega rding the information in this publication or regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. further, davicom makes no warranty of merchantability or fitness for any purpose. davicom reserves the right to halt production or alter the specifications and prices at any time without notice. accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. products described herein are intended for use in normal commercial applications. applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by davicom for such applications. please note that application circuits illustrated in this document are for reference purposes only. davicom?s terms and conditions printed on the order acknowledgment govern all sales by davicom. davicom will not be bound by any terms inconsistent with these unless davicom agrees otherwise in writing. acceptance of the buyer?s orders shall be based on these terms. company overview davicom semiconductor inc. develops and manufactures integrated circuits for integration into data communication products. our mission is to design and produce ic products that are the industry?s best value for data, audio, video, and internet/intranet applications. to achieve this goal, we have built an organization that is able to develop chipsets in response to the evolving technology requirements of our customers while still delivering products that meet their cost requirements. products we offer only products that satisfy high performance requirements and which are compatible with major hardware and software standards. our currently available and soon to be released products are based on our proprietary designs and deliver high quality, high performance chipsets that comply with modem communication standards and ethernet networking standards. contact windows for additional information about davicom products, contact the sales department at: headquarters hsin-chu office: no. 6 li-hsin rd. vi, science park, hsin-chu,taiwan, r.o.c. tel: + 886-3-5798797 fax: + 886-3-5646929 http://www.davicom.com.tw warning conditions beyond those listed for the absolute maximum may destroy or damage the products. in addition, conditions for sustai ned periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/o r function.

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